1. Field
The following description relates to a processor with a reconfigurable architecture, and more particularly, to configuration memory access technology in a reconfigurable processor.
2. Description of the Related Art
The concept of conventional reconfigurable computing is based on a processor with reconfigurable hardware devices that are arranged in an array. Behavior of such reconfigurable hardware devices, including data flow between each of the reconfigurable hardware devices, is tailored to perform a specific task. A reconfigurable processor may have a superior processing performance comparable with dedicated hardware.
A reconfigurable hardware may also be known as a processing element (PE). A size of such a PE is called ‘granularity.’ A PE whose granularity is large may be termed to ‘have a Coarse-Grained Reconfigurable Architecture (CGRA),’ and a PE whose granularity is small may be termed to ‘have a Fine-Grained Reconfigurable Architecture.’
An internal memory controller of a CGRA processor reads, per clock cycle, instructions corresponding to all PEs from a configuration memory, and supplies the instructions to the CGRA processor. However, if a large number of PEs exists, or if a word is particularly long, a configuration memory access frequency may increase, which results in an increase of power consumption of the processor.